The present invention pertains to the field of computer systems, and, in particular, an interface between hub components within a computer system.
Prior computer systems typically rely on busses such as the Peripheral Component Interconnect (PCI) bus adhering to a Specification Revision 2.2 bus developed by the PCI Special Interest Group of Portland Oregon, to allow computer system chipset components to communicate with one another. For example, a transaction originating at a processor and intended for a disk drive might first be delivered to a first chipset component that serves as an intermediary between the processor bus and a PCI bus. The first chipset component would then deliver the transaction over the PCI bus to a second system chipset component which would then deliver the transaction to the disk drive.
Busses such as the PCI bus also provide for communication with other computer system devices such as graphics controllers and network adapters. Because busses such as the PCI bus must interface with a variety of component types, each with varying requirements, the busses are not necessarily optimized for allowing communication between chipset components. Further, chipset manufacturers who rely on standardized busses such as the PCI bus must adhere to bus standards in order to ensure compatibility with other components, and are not at liberty to make substantial changes in how the chipset components communicate with each other.
Another issue that faces chipset component manufacturers in designing and manufacturing chipset components is the need to conform to standardized supply and signaling voltages when relying on busses such as PCI for communication between chipset components, thereby locking the manufacturers into certain design practices and manufacturing technologies. Therefore, it would be desirable to provide a flexible interface that provides optimal communication between chipset components.
In addition, it would be desirable to provide an improved method and apparatus for initializing components coupled to such an interface. More specifically, if components coupled via an interface, are transitioning from a low power state to a higher power state, each component may have to wait for a predetermined period of time to lapse before they may begin transmitting and receiving data across the interface. Such a technique is inefficient because both components may both be awake prior the lapsing of the predetermined period of time. As a result, the components would have to unecessarily wait the additional length of time before they could transmit data. Alternatively, the predetermined period of time may not be long enough for one of the components to awake. Therefore, there is a need for an improved method of initializing an interface between to computer components.
The present invention provides a first control hub component, having a first logic to synchronize an internal clock generator with an external clock generator in response to the external clock generator transitioning to a high power state. In response to the internal clock generator being synchronized with the external clock generator, the first control hub transmits a request packet to a second control hub via an interface. The first logic monitors the interface for receipt of a completion packet in reply to the request packet, wherein in response to the completion packet, the first control hub is operable to continue communication with the second hub via the interface.